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gp2010 gps receiver rf front end july2006 the gp2010 is a second generation rf front-end for global positioning system (gps) receivers. the gp2010 uses many innovative design techniques and a leading-edge bipolar process to offer a low power, low cost and high reliability rf front end solution . the gp2010 is designed to operate from either 3 or 5 volt power supplies. the input to the device is the l1 (1575.42mhz) coarse- acquisition (c/a) code global positioning signal from an antenna (via a low-noise pre-amplifier). the output is 2-bit quantised for subsequent signal processing in the digital domain. the gp2010 contains an on-chip synthesiser, mixers, agc and a quantiser which provides sign and magnitude digital outputs. a minimum of external components is required to make a complete gps front-end. the device has been designed to operate with the gp2021 12-channel global positioning correlator, also available from zarlink semiconductor. features low voltage operation (3v - 5v) low power - 200mw typ. (3v supply) c/a code compatible on-chip pll including complete vco triple conversion receiver 44-lead surface mount quad flat-pack package sign and magnitude digital outputs compatible with gp2021 cmos correlator applications c/a code global positioning by satellite receivers time standards navigation ?surveying pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 name if output pll filter 1 pll filter 2 v ee (osc) v cc (osc) v ee (osc) v ee (reg) pref preset v ee (io) clk mag sign opc ik- opc ik+ v dd (io) pd n test ld v ee (dig) agc - agc + name v cc (dig) ref 2 ref 1 v cc (rf) v ee (rf) v ee (rf) rf input v ee (rf) v ee (rf) v cc (rf) o/p 1- o/p 1+ v cc (2) i/p 2- i/p 2+ v ee (if) v ee (if) o/p 2- o/p 2+ v cc (3) i/p 3- i/p 3+ pin 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 fig. 1 pin connections - top view gp 2010 22 21 20 19 18 17 16 15 14 13 12 34 35 36 37 38 39 40 41 42 43 44 11 10 9 8 7 6 5 4 3 2 1 23 24 25 26 27 28 29 30 31 32 33 gp 44 related products and publications ds4374 ds4057 an4855 ab5202 data reference part description small rf format front end gp2000 gps receiver hardware design twelve-channel correlator gp2000 gps receiver hardware design gp2010/gp2015: using murata safja35m4wc0z00 saw filter gp2015 gp2021 app. note app. brief 1 zarlink semiconductor inc. zarlink, zl and the zarlink semiconductor logo are trademarks of zarlink semiconductor inc. copy right 2002 -2006, zarlink semiconductor inc. all rights reserved. ordering information gp2010/ig/gpbn 44 pin mqfp trays, bake & drypack gp2010/ig/gp2n 44 pin mqfp* trays, bake & drypack *pb free matte tin -40 to 85 c
2 gp2010 absolute maximum ratings (non-simultaneous) max. supply voltage 7v max. rf input +15dbm max. voltage on any pin v cc /v dd + 0.5v except ld (pin 19) and preset (pin 9), which are 5.5v min. voltage on any pin v ee - 0.5v storage temperature -65 c to +150 c operation junction temperature -40 c to +150 c 10mhz reference input 1.5v pk -pk 0 000004ojo0000j0 0000000t00j00 00000jfaftz400jto4h 0t00000000 -jhoe00004tozk0e000 00000t00000 0004ojo000000 0000000000e0 0oo00000t0- 0000-000jzoot 0000-00,0jw00jaftz400 000000000t00 -00j0000-e 000000 t 00000000 000000jzo000000 hftz40t0000000- 0-0000000 t 0000400000 000j000jtt0000 000000000 000000,00hfzoooe 00wt00000000 00t000400000 0000000hjtjjj0000 00ztho0t00000-00000 00000ztho0t000e 00j ?
3 gp2010 power-down capability a power down function is provided on the gp2010, to limit power consumption. this powers down the majority of the circuit except the power-on reset function (see below). if the power down feature is not required, the power- down input, pd n (pin 17), should be connected to 0v dc (=vee/ground). power-on reset function the gp2010 includes a voltage detector which operates from the digital interface supply. this circuit is used to produce a ttl logic low output while the gps receiver power supply is switching on, and produces a logic high output when the power supply voltage has achieved a nominal value. this output can be used to disable the gp2021 correlator while the power supply is switching on. an internal bandgap reference of approximately +1.21v is compared with the voltage on a sense pin, pref (pin 8); when the voltage on this pin exceeds the reference, a ttl logic high level appears at the power-on reset output, preset (pin 9). thus, if the sense input voltage is derived from an external resistive divider from the digital interface supply, v dd (io) (pin 16), such that the sense voltage at nominal v cc is v s , then the supply threshold, vcc(thresh), at which the preset output goes to logic high is:- for a v cc (nom) of 5.0v, v cc (thresh) may be set to approx. 4.0v, giving v s of 1.5v. for a v cc (nom) of 3.0v, v cc (thresh) may be set to approx. 2.4v, giving v s of 1.5v. additional information all the digital inputs and outputs can use a separate power supply to help prevent digital switching transitions interacting with the analog sections of the device, and as an additional precaution, the digital inputs and outputs are on the opposite side of the device to the critical analog pins. the if output is fed to a 2-bit quantiser which provides sign and magnitude (msb and lsb) outputs. the magnitude data controls the agc loop, such that on average the magnitude bit is set (high) 30% of the time. the agc time constant is set by an external capacitor. the sign and magnitude data, sign (pin 13) and mag (pin 12), are latched by the rising edge of the sample clock, clk (pin 11), which is normally derived from the correlator; the gp2021 provides a 5.714mhz (=40/7) clock, giving a sampled if centred on 1.405mhz. the digital interface circuits use a separate power-supply, v dd (io), which would normally be shared with the correlator to minimise crosstalk between the analog and digital sections of the device. on-chip phase-locked loop synthesiser all of the local oscillator signals are derived from an on chip phase locked loop synthesiser. this includes a 1400mhz vco complete with on-chip tank circuit, dividers and phase detector, with external loop filter components. a 10.000mhz reference frequency is required for the pll. this can be achieved by attaching an external 10.000mhz crystal to the on-chip pll reference oscillator (see figure 5). however in most applications the user will need an external source, such as a tcxo, to provide greater frequency stability (see figure 6). an external reference should be ac coupled to ref2 (pin 24); ref 1 (pin 25) should be left open circuit. the three local oscillator signals 1400mhz, 140.0mhz and 31.11mhz are derived from the 1400mhz synthesiser output. the synthesiser also provides a 40 mhz balanced differential output clock (pins 14 & 15) which can be used to clock the gp2021 correlator. the clock is a low level differential signal which helps minimise interference with the analog areas of the circuit. a pll lock-detect output, ld (pin 19), is also provided, which is logic high when the pll is phase- locked to the 10.000mhz reference signal. the vco power-supply incorporates an on-chip regulator to improve the noise-immunity of the pll. this feature is only available when operating with a 5 volt (nominal) supply which is regulated to 3.3 volts internally. this internal regulated supply is referenced to v cc (osc) (pin 5). figure 7 shows the required connections for both 3 volt and 5 volt operation. a further feature of the circuit is the test input (pin 18). when this input is held high the pll is unlocked with the vco at its maximum frequency. v s = v cc (nom) x 1.21 v cc (thresh)
4 gp2010 electrical characteristics the electrical characteristics are guaranteed over the following range of operating conditions (see fig. 3 for test circuit): cf.c ccc ? ? ? ? ? ? ? ?
5 gp2010 mhz mhz v mhz/v v/rad v pk-pk k ? ms db v v a a v v ns v v mv p-p % v v v a ,0zw ,0aw 04z ,0jjw 000,0aw ,0aw 0jje0jae0j% 00 00 0jhe0j4 00-otf 00otf 00jfe0000jf ?
6 gp2010 pin descriptions all v ee and v cc /v dd pins should be connected to ensure reliable operation pin no. signal name input/output description 1 ifoutput output if test output. connected to output of stage 3 prior to the a to d converter. a series 1k ?
7 gp2010 pin no. signal name input/output description 17 pdn input power-down control input. a ttl compatible input, which when set to logic high, will disable all of the gp2010 functions, except the power-on reset block. useful to reduce the total power consumption of the gp2010. if this feature is not required, the pin should be connected to 0v (v ee /gnd). 18 test input test control input - disable pll. a ttl compatible input, which when set to logic high, will disable the on-chip pll, by disconnecting the divided-down vco signal to the phase-detector. the vco will free run at its upper range of frequency operation. if this feature is not required, the pin should be connected to 0v (v ee /gnd). 19 ld output pll lock detect output. a ttl compatible output, which indicates if the pll is phase- locked to the pll reference oscillator. will become logic high only when phase-lock is achieved. 20 v ee (dig) input negative supply to the pll and a to d converter. 21 agc- output agc capacitor output - inverse phase. one side of a balanced output from the agc block within if stage 3, to which an external capacitor is connected to set the agc time-constant. 22 agc+ output agc capacitor output - true phase. one side of a balanced output from the agc block within if stage 3, to which an external capacitor is connected to set the agc time-constant. 23 v cc (dig) input positive supply to the pll and a to d converter. 24 ref 2 input 10.000mhz pll reference signal input . input to which an externally generated 10.000mhz pll reference signal should be ac coupled, if an external pll reference frequency source (e.g tcxo) is used (see fig. 6). if no external reference is used, this pin forms part of the on- chip pll reference oscillator, in conjunction with an external 10.000mhz crystal (see fig. 5). 25 ref 1 input pll reference oscillator auxillary connection. used in conjunction with pin 24 (ref 2) to allow a 10.000mhz external crystal to provide the pll reference signal if no external pll reference frequency source (e.g tcxo) is used. this pin should not be connected if an external tcxo is being used (see fig. 5). 26, 32 v cc (rf) input positive supply to the rf input and stage 1 if mixer. both pins 26 & 32 (v cc (rf)) are connected internally, but must both be connected to v cc externally, to keep series inductance to a minimum. 27, 28, v ee (rf) input negative supply to the rf input and stage 1 if mixer. 30, 31 pins 27, 28, 30 & 31 are all connected internally, but must all be connected to 0v (v ee /gnd) externally, to keep series inductance to a minimum.
8 gp2010 pin no. signal name input/output description 29 rf input input rf input. the gps rf input signal @ 1575.42mhz from an external antenna with lna and filter is connected to this pin via an input-matching network (see fig.4). 33 o/p 1- output stage 1 mixer output @ 175.42mhz - inverse phase. one of a balanced output from first stage if mixer, to which one input of an external balanced 175mhz bandpass filter is connected. external dc biasing is required via an inductor connected to v cc (rf) - the value of which is dependent on the filter used. 34 o/p 1+ output stage 1 mixer output @ 175.42mhz - true phase. second of a balanced output from first stage if mixer, to which the second input of an external balanced 175mhz bandpass filter is connected. external dc biasing is required via an inductor connected to v cc (rf) - the value of which is dependent on the filter used. 35 v cc (2) input positive supply to the stage 2 if mixer. 36 i/p 2- input stage 2 mixer input @ 175.42mhz - inverse phase. one of a balanced input to the second stage if mixer, to which one of the balanced signal outputs from the external 175mhz bandpass filter is connected. 37 i/p 2+ input stage 2 mixer input @ 175.42mhz - true phase. second of a balanced input to the second stage if mixer, to which the second of the balanced signal outputs from the external 175mhz bandpass filter is connected. 38,39 v ee (if) input negative supply to the stage 2 if mixer, and stage 3 if block. 40 o/p 2- output stage 2 mixer output @ 35.42mhz - inverse phase. one of a balanced output from second stage if mixer, to which one input of an external balanced 35.42mhz bandpass filter is connected. external dc biasing is required via an inductor connected to v cc . (see note 3) 41 o/p 2+ output stage 2 mixer output @ 35.42mhz - true phase. second of a balanced output from second stage if mixer, to which the second input of an external balanced 35.42mhz bandpass filter is connected. external dc biasing is required via an inductor connected to v cc . (see note 3) 42 v cc (3) input positive supply to the stage 3 if mixer. 43 i/p 3- input stage 3 mixer input @ 35.42mhz - inverse phase. one of a balanced input to the third stage if mixer, to which one of the balanced signal outputs from the external 35.42mhz bandpass filter is connected. (see note 3) 44 i/p 3+ input stage 3 mixer input @ 35.42mhz - true phase. second of a balanced input to the third stage if mixer, to which the second of the balanced signal outputs from the external 35.42mhz bandpass filter is connected. (see note 3)
9 gp2010 notes on pin descriptions 1). both pins 4 & 6 (v ee (osc)) are connected internally. if the vco regulator is used (v cc = +5.00v nominal) then both pins 4 & 6 must be left floating, with either pin de-coupled to v cc (osc) with a 100nf capacitor. in this configuration, the dc output level of the regulator can be monitored from v ee (osc), with respect to v cc (osc) - not 0v (v ee /gnd). for operation at v cc <+4.0v, the vco regulator cannot be used, and both v ee (osc) pins must be shorted to v ee (reg) (pin 7) - see fig. 7. 2). the digital interface supply is independent from all the other supply pins, allowing supply separation to reduce the likelih ood of undesirable digital signals interfering with the if strip. (note the maximum allowable power supply differential in the electrical characteristics - page 4). 3). the 35.42mhz bandpass filter should have a bandwidth of approx 2.0mhz. lh power down normal operation powered down test normal operation test control signals operating notes a typical application circuit is shown in figure 4 with the gp2010 front-end interfaced to the gp2021 12 channel correlator integrated circuit. the rf input has an unmatched input impedance (see page 4). the rf input matching com- ponents cs and cp should be mounted as close to the rf input as possible: also the vee(rf) tracks must be kept as short as possible. a saw may be used as a 175.42mhz filter, but this can be replaced by a simpler coupled-tuned lc filter if there is no critical out-of band jamming immunity require- ment. the dc bias to mixer 1 is provided via inductors l1 and l2, which may form part of the 175.42mhz filter. the output of mixer 2 requires an external dc bias, achieved with inductors l3 and l4, which also serve to tune out the input capacitance of the 35.42mhz saw filter. the output of the saw is tuned with inductor l5. the agc capacitor (cagc) determines the agc time-constant. the pll loop filter components are selected to give a pll loop bandwidth of approx. 10khz. the if output is normally used for test-purposes only, but is available to the user if required. typically a low noise preamplifier (gain >+15db) is used, and may be located with a remote antenna. fig. 3 gp2010 test circuit stage 2 stage 3 agc control m1 m2 m3 m4 rf input cs stage 1 output 175 mhz stage 2 input 175 mhz stage 2 output 35 mhz stage 3 input 35 mhz c1 c2 r1 if output clk sign mag cagc opclk ld ref 2 test pdn 1 12 22 pll loop filter preset pref 21 13 11 44 43 41 40 37 36 34 33 29 2 cp 3 14 15 19 pll synthesiser 24 18 power down 17 power detect 98 agc control adc stage 3 m4 m3 stage 2 m2 m1 stage 1 m1 - 4 = matching networks, incorporating balun transformers c1 = 470nf c2 = 10nf r1 = 270 ?
10 gp2010 fig. 4 gp2010 typical application fig. 5 crystal reference connections (25) (24) 33pf 10.000mhz crystal ref 1 ref 2 gp2010 22pf gp2010 front-end 44 pin 175mhz filter l4 saw filter l3 l1 l2 l5 cs cp cagc =0.1uf gp2021 correlator 80 pin clk_t clk_i sign 0 mag 0 pll lock 15 14 11 samp clk 13 12 19 9 22 27,28, 30,31 21 29 33 34 36 37 40 41 43 44 vcc ref2 10mhz i/p pll loop filter c1 = 0.47uf r1 = 270 ? ? ?
11 gp2010 fig. 6 tcxo reference connections (25) (24) ref 1 ref 2 gp2010 nc 47nf 10.000mhz tcxo rb ra ra & rb set to reduce tcxo o/p to required level fig. 7 vco power-supply connections gp2010 gp2010 100nf v ccosc v eeosc v eereg (5) (4) (6) (7) 3v 0v no vco regulator needed v ccosc v eeosc v eereg (5) (4) (6) (7) 5v 0v using vco regulator with vcc > +4.0v
12 gp2010 typical characteristics of the gp2010 gps receiver rf front-end the gp2010 has been characterised to guarantee reliable operation over the industrial temperature range (-40
13 gp2010 fig. 10 supply current - digital interface - normal mode fig. 11 supply current - digital interface - power-down mode case temp(
14 gp2010 fig. 13 on-chip phase-locked-loop synthesiser loop gain case temp(
15 gp2010 fig. 14 on-chip phase-locked-loop synthesiser phase-detector gain case temp(
16 gp2010 fig. 16 on-chip phase-locked-loop synthesiser - phase-noise of vco producing 1400mhz cw signal at 10khz offset (15khz pll loop bandwidth) fig. 17 on-chip phase-locked-loop synthesiser - phase-noise of vco producing 1400mhz cw signal at 100khz offset (15khz pll loop bandwidth) case temp (
17 gp2010 fig. 18 frontend/mixer 1 small-signal conversion gain - rf i/p frequency at 1575.42mhz case temp (
18 gp2010 fig. 20 frontend/mixer 1 image rejection - rf i/p frequency at 1224.58mhz case temp (
19 gp2010 fig. 22 stage 2/mixer 2 input level for 1db conversion gain-compression - stage 2 i/p frequency at 175.42mhz case temp (
20 gp2010 fig. 25 duty-cycle of mag digital output (pin 12), sampled at 5.71mhz in a typical application circuit - rf i/p signal = 1575.42mhz cw, -85dbm - equivalent to 26db excess noise from a typical gps antenna case temp(
21 gp2010 fig. 26 duty-cycle of sign digital output (pin 13), sampled at 5.71mhz in a typical application circuit - rf i/p signal = 1575.42mhz cw, -85dbm - equivalent to 26db excess noise from a typical gps antenna case temp(
22 gp2010 fig. 28 typical matched rf i/p impedance between 1000mhz and 2000mhz rf i/p level @ -40dbm -j 0.5 -j 1 -j 3 j 0.5 j 1 j 3 0

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